A silicon single crystal is manufactured by pulling using the CZ (Czochralski) method. The pulled silicon single crystal ingot is sliced into silicon wafers. A semiconductor device is fabricated through a device process to form a device layer on the surface of a silicon wafer.
However, a crystal defect referred to as the “grown-in defect” (defect incurred during the crystal growth) occurs in the course of the growth of a silicon single crystal.
Along with recent progress of integration and refinement of semiconductor circuits, the presence of such grow-in defects has become intolerable in the vicinity of a surface layer of a silicon wafer where a device is fabricated. Thus, studies are being conducted on the possibility of producing a defect-free crystal.
In general, there are the following three types of crystal defects which may be included in a silicon single crystal and deteriorate device characteristics.
a) Void defect generated by aggregation of vacancies and referred to as COP (Crystal Originated Particles) or the like
b) OSF (Oxidation Induced Stacking Fault).
c) Dislocation loop clusters generated by aggregation of interstitial silicon (also known as interstitial silicon dislocation defects, or I-defects)
A defect-free silicon single crystal is recognized or defined as a crystal not including or substantially not including any of the three types of defects.
It is known that the generation behaviors of the above-mentioned three types of defects vary depending on growth conditions as described below. Description will be made with reference to FIG. 1A. In FIG. 1A, the horizontal axis represents the growth condition V/G1. Assuming that G1 is fixed, it can be considered as a function of the growth rate V. The vertical axis in FIG. 1A represents the point defect concentration |(Cv−Cv,eg)−(Ci−Ci,eg)|, where Cv denotes a hole concentration in a silicon single crystal 10, and CV,eq denotes a thermal equilibrium concentration of holes in the silicon single crystal 10. When holes are excessively incorporated, the degree of supersaturation of the holes (CV/CV,eq) will increase along with decrease in temperature. Void defects are generated upon the degree of supersaturation of the holes reaching a critical value. Ci denotes an interstitial silicon concentration in the silicon single crystal 10, and Ci,eq denotes a thermal equilibrium concentration of interstitial silicon in the silicon single crystal 10.
In FIG. 1A, 100A, 100B, 100C, 100D, and 100E conceptually illustrate sizes and densities of various types of defects generated between a surface center and an edge of a silicon wafer 100 obtained from the silicon single crystal 10. The surface center and the edge of the silicon wafer 100 correspond to a crystal center and a crystal edge (crystal periphery) of the silicon single crystal 10, respectively. FIGS. 1B, 1C, 11, and 1E are conceptual diagrams of the surface of the silicon wafer 100 corresponding to 100A, 100B, 100C, 100D, and 100E, respectively, and conceptually illustrating the sizes and densities of various types of defects occurring in the wafer surface.
i) When the growth rate V is high, as shown by 100A and 100B in FIGS. 1A through 1E, hole-type point defects becomes excessive and only void defects are generated in the silicon single crystal 10.
ii) When the growth rate V is decreased, as shown by 100C, a ring-shaped OSF (R-OSF) is generated near the periphery of the silicon single crystal 10 and void defects are located inside the R-OSF portion.
iii) When the growth rate V is decreased further, as shown by 100D, the radius of the ring-shaped OSF (R-OSF) becomes smaller, and a region where no defect is present is produced outside the ring-shaped OSF portion while void defects are present inside the R-OSF portion.
iv) When the growth rate V is decreased still further, as shown by 100E, dislocation loop clusters are present all over the silicon single crystal 10.
It is believed that the phenomena as described above occur for the reason that along with the decrease in the growth rate V the silicon single crystal 10 shifts from the state where excessive hole-type point defects are present to the state where excessive interstitial-type point defects are present.
In FIG. 1A, the region where void defects are present at a high density is referred to as the V-rich region (hole-type point defect rich region), and as the I-rich region (region dominated by interstitial-type point defects).
Among the three types of defects described above, the void defects in a) are particularly required to be minimized since they may cause faulty element isolation or the like in refined devices.
The void defects are produced when atomic vacancies (point defects) incorporated from a silicon melt during crystal growth agglomerate as a result of reaching a critical supersaturation during crystal cooling, and are called LPD (laser particle defect), COP (crystal oriented particle), FPD (flow pattern defect), LSTD (laser scattering tomography defect), and so forth depending on methods for detecting such defects.
As shown by 100A and 100B in FIG. 1A, when the silicon single crystal 10 is pulled under conditions such that the V-rich region in which the void defects are present all over the silicon wafer is produced, there exist COPs or the like caused by the void defects exposed in the surface of the silicon wafer 100 obtained from the silicon single crystal 10. This will incur deterioration of the oxide film pressure resistance characteristic, resulting in deterioration of the physical properties of the device. For example, faulty element isolation may occur in a refined device. Therefore, the reduction of the void defects of a) among the three types of defects described above is particularly imperative. Nowadays, the device line width has been decreased to an extent substantially corresponding to the COP size, and hence the reduction of the COPs or the like is particularly necessary.
Of course, there will be no problem if the silicon single crystal 10 is manufactured defect-free. However, very precise pulling control is required to manufacture such a silicon single crystal, incurring a problem of poor productivity.
It has been conventionally believed that, when the silicon single crystal 10 is pulled under conditions such that an I-rich region in which the interstitial-type point defects are present all over the silicon wafer is produced, there will be substantially no COPs and desirable oxide film pressure resistance characteristic can be provided without deterioration of the device characteristics.
Description will be made of related arts relating to the present invention and disclosed in patent documents.
(Related Art 1)
Patent Document 1 (Japanese Patent Application Laid-Open No. 11-349394) describes an invention in which a silicon single crystal is doped with nitrogen and pulled under pulling conditions corresponding to the I-rich region.
(Related Art 2)
Patent Document 2 (Japanese Patent Application Laid-Open No. 10-291892) describes that oxygen incorporated in a silicon single crystal increases the strength of the crystal and prevents the dislocation movement, reducing the wafer deformation (warpage) caused by heat treatment.
(Related Art 3)
Patent Document 3 (Japanese Patent Application Laid-Open No. 2002-226295) describes that resistance to slip can be expected by incorporating a large amount of oxygen into a silicon single crystal.